1) Field of the Invention
The technology presented herein generally relates to semiconductor devices, and more particularly to a semiconductor device that has high flatness of the interlayer insulating film. The technology also relates to a method for producing the semiconductor device.
2) Description of the Related Art
With high integration and large capacitance of integrated circuit elements, the wirings on semiconductor devices are becoming miniaturized, and thus there is a need for a method for forming wirings and plugs between wirings with higher flatness. A widely used method in view of the need is such that after forming a via-hole, metal such as tungsten accumulates and is filled in the via-hole, and by removing the metal over the interlayer insulating film by chemical mechanical polishing (hereinafter referred to as CMP), a via-hole plug is formed.
FIG. 3 is a cross-section showing an example of a conventional method for forming a via-hole plug by CMP. Referring to FIG. 3(A), insulating film 2 is formed on semiconductor substrate 1. On insulating film 2, lower-layer wiring 3 is formed. Interlayer insulating film 4 is formed to cover lower-layer wiring 3, and in interlayer insulating film 4, by using photolithography and etching, via-hole 6a that exposes the surface of lower-layer wiring 3 is formed. By the chemical vapor deposition (CVD) method, conductive film 8 of, for example, a tungsten film accumulates over the entire surface to fill via-hole 6a. There is a case where for improvement of adhesion, a titanium nitride film or the like accumulates prior to accumulation of conductive film 8 to have a plurality of conductive-film structures.
Subsequently referring to FIGS. 3(A) and 3(B), by removing conductive film 8 over interlayer insulating film 4 by CMP, via-hole plug 8a is formed with high flatness.
However, the above-described CMP, used when forming via-hole plugs between wirings, is problematic in that CMP is affected by the roughness and fineness of arranged via-hole plugs, causing variation in the polishing rate of conductive film 8. This will be described below.
FIG. 4 is a view showing the problem of CMP encountered when there is roughness and fineness of arrangement of via-holes, that is, when there are region H where via-holes are densely formed and region L where no via-holes exist.
Referring to FIG. 4(A), insulating film 2 is formed on semiconductor substrate 1. On insulating film 2, lower-layer wirings 3 are formed. Interlayer insulating film 4 is formed to cover lower-layer wirings 3, and in interlayer insulating film 4, by using photolithography and etching, via-holes 6a that expose the surfaces of lower-layer wirings 3 are formed. In this example, region H where via-holes 6a exist densely and region L where no via-holes exist will be described.
Referring to FIG. 4(B), by the chemical vapor deposition (CVD) method, conductive film 8 of, for example, a tungsten film accumulates over the entire surface to fill via-holes 6a. There is a case where for improvement of adhesion, titanium nitride film 9 or the like accumulates prior to accumulation of conductive film 8 to have a plurality of conductive-film structures. Subsequently, referring to FIGS. 4(B) and 4(C), by removing conductive film 8 and titanium nitride film 9 over interlayer insulating film 4 by CMP, via-hole plugs 8a are formed.
In this case, referring to FIG. 4(C), a phenomenon called erosion occurs, and fang form 12 is locally observed. Erosion means that a portion of the insulating film that is not supposed to be polished is polished by CMP, a phenomenon typically seen in dense wirings and wide wirings.
Because of the erosion phenomenon, in region L, where no via-hole plugs are provided, in comparison with region H, where via-hole plugs 8a are provided, the polishing rate of conductive film 8 is significantly reduced, making the difference between the polishing rates even larger. Because of the erosion phenomenon, after forming via-hole plugs 8a, trouble that the flatness of interlayer insulating film 4 is impaired is caused. In the figure, reference numeral 11 indicates the amount of depression because of the erosion phenomenon. In addition, around the interface portion between region L, where no via-hole plugs 8a are provided, and region H, where via-hole plugs 8a are provided, large fang form 12 is locally observed, and also the flatness of interlayer insulating film 4 is greatly impaired. In the figure, reference numeral 13 indicates the amount of fang.
To obtain flatness of interlayer insulating film 4 at the interface portion between region L, where no via-hole plugs are provided, and region H, where via-hole plugs 8a are provided, it is effective to provide a dummy via-hole.
FIG. 5(A) is a cross section of a conventional semiconductor device in which, in view of the above point, dummy via-holes 103a are formed in the interface portion between the region where no via-hole plugs are provided and the region where via-hole plugs are provided (see, for example, Japanese Patent Application Publication No. 8-222632). In the figure, reference numeral 101 indicates a lower-layer wiring, 102 indicates an interlayer insulating film, 103 indicates a via-hole, 104 indicates an adhesive layer, 105 indicates a conductive film, 106 indicates a via-hole plug, and 106a indicates a dummy via-hole plug.
Referring to FIG. 5(B), according to this method, at the time of forming via-hole plugs 106 by CMP, since dummy via-hole plugs 106a are provided in a rough region where there is a wide interval between via-hole plugs, there is no depression caused by over-polishing.
However, with the method described in FIG. 5, when there are regions with various via-hole plug densities, it is difficult to provide dummy via-hole plugs with uniform density, and consequently, it is difficult to eliminate depression caused by over-polishing. In addition, with this method, it is impossible to effectively remove a fang form encountered in the interface portion between the region where no via-hole plugs are provided and the region where via-hole plugs are provided, resulting in the problem that in the end portion of a region with a particularly high via-hole plug density, the surface of the interlayer insulating film cannot be made flat. If a flat surface cannot be obtained for the interlayer insulating film, the processing accuracy of an upper-layer wiring pattern and the reliability of patterning are reduced.